In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits (ICs), such as application specific integrated circuit (ASIC) chips, central processing unit (CPU) chips, digital signal processor (DSP) chips and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices, among other things. A SOC device integrates into a single chip all (or nearly all) of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, and the like).
An important criterion in evaluating the performance of an electronic device is power consumption. Minimizing power consumption has long been an important design consideration in portable devices that operate on battery power. Since maximizing battery life is a critical objective in a portable device, it is essential to minimize the power consumption of ICs used in the portable device. More recently, minimizing power consumption has also become more important in electronic devices that are not portable. The increased use of a wide variety of electronic products by consumers and businesses has caused corresponding increases in the electrical utility bills of homeowners and business operators. The increased use of electronic products also is a major contributor to the increased electrical demand that has caused highly publicized power shortages in the United States, particularly California.
Generally speaking, if an electronic component operates at a slower speed, it uses less power because there are less power-consuming signal level transitions in a given time period. Also, at slower speeds, lower power supply voltages can be used because gate switching speeds are not as critical. To minimize power consumption, many complex electronic components, such as CPUs and DSPs, adaptively change the clock speed to different operating frequencies according to the requirements of the task being performed. The range of clock frequencies may be quite large.
In many electronic systems, the clock signals that drive an integrated circuit are generated by a frequency synthesizer phase-locked loop (PLL). Frequency synthesizer PLLs are well known to those skilled in the art and have been extensively written about. The dynamic performance of the frequency synthesizer PLL is dependent on several parameters, including the natural frequency (Fn), the damping factor (DF), the crossover frequency (F0) and the ratio of the comparison frequency (Fc) to the crossover frequency. The first three parameters depend on the voltage controlled oscillator (VCO) gain (K0), the F/B (N) divider value, the charge pump current (Ic), and the loop filter components. The last parameter (i.e., the ratio of comparison frequency to crossover frequency) is dependent on the input divider (M) value, as well as the frequency of the input clock itself.
In a frequency synthesizer PLL in which different values of M are used as well as where input clock frequencies over a wide range could be used, there is a need for method and apparatuses that can ensure the stability of the loop over this wide operating range.